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vip, vip-8 versatile isdn port peb 20590 version 2.1 peb 20591 version 2.1 data sheet, ds4, march 2001 wired communications never stop thinking.
edition 2001-03-01 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications p r e l i m i n a r y vip, vip-8 versatile isdn port peb 20590 version 2.1 peb 20591 version 2.1 data sheet, ds4, march 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag. peb 20590, peb 20591 preliminary revision history: 2001-03-01 ds4 previous version: 01.00 page subjects (major changes since last revision) page 15 pull-ups for the signals tms, tdi, trst page 34 id-code for tap controller page 29 maximum wander tolerance page 35 vip version register page 46 primary inductance for recommended s/t transformer page 46 external s/t receiver circuitry page 38 - page 45 electrical characteristics note: this revision history is not 100% complete.
peb 20590 peb 20591 table of contents page data sheet 2001-03-01 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 logic symbol diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 overview of interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 u pn line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 u pn transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.3 receive pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.4 receive signal oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 s/t line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3.1 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 s/t transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3 receive clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.3.1 lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3.2 lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.3.4 reference clock selection in lt-t mode . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.5 receive signal oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6 elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4 iom-2000 interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.1 iom-2000 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.1.1 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5 jtag boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 analog test loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.5 monitoring of code violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 recommended 15.36-mhz crystal parameters . . . . . . . . . . . . . . . . . . . . 41
peb 20590 peb 20591 table of contents page data sheet 2001-03-01 5.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.7 refclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.8 upn interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.9 iom-2000 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.10 jtag boundary scan test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.11 u pn transmitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.12 s/t transmitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 vip external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.1 recommended line transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1.2 u pn interface external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.3 s/t interface external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 wiring configurations in lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 loop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
peb 20590 peb 20591 list of figures page data sheet 2001-03-01 figure 1 top-level block diagram of the vip . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2 logic symbol peb 20590 (72 of 80 pins used) . . . . . . . . . . . . . . . . . . . 6 figure 3 logic symbol peb 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4 vip in mixed s/t and u pn line cards (e.g. 8 s/t and 16 u pn ). . . . . . . 7 figure 5 vip in a small pbx solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6 delic-pb and vip in a pc card for 8/16 s/t interfaces . . . . . . . . . . . 8 figure 7 pin diagram, peb 20590 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8 pin diagram, peb 20591 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9 u pn interface frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10 ami coding on the u pn interface in vip . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 transceiver functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 equalizer effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13 receive signal oversampling on u pn interface . . . . . . . . . . . . . . . . . 22 figure 14 frame structure at reference points s and t (itu-t i.430) . . . . . . . . 23 figure 15 s/t interface line code (without code violation) . . . . . . . . . . . . . . . . 24 figure 16 receiver functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17 clock recovery in lt-t mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18 lt-t reference clock channel selection for cascaded vips. . . . . . . 28 figure 19 receive signal oversampling in s/t receiver . . . . . . . . . . . . . . . . . . 29 figure 20 overview of iom-2000 interface structure (example with one vip) . . 30 figure 21 iom-2000 data sequence (1 vip with 8 channels) . . . . . . . . . . . . . . 32 figure 22 iom-2000 data order (3 vips with 24 channels) . . . . . . . . . . . . . . . . 33 figure 23 recommended oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24 input/output wave form for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 25 iom-2000 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 26 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 27 1:1 transformer model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 28 external transceiver circuitry of the vip in u pn mode . . . . . . . . . . . . 47 figure 29 overview of external circuitry of the vip in s/t mode . . . . . . . . . . . . 47 figure 30 external s/t transmitter circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 31 external s/t receiver circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 32 wiring configurations in user premises (lt-s mode) . . . . . . . . . . . . . 49 figure 33 internal and external loop-back modes . . . . . . . . . . . . . . . . . . . . . . . 50
peb 20590 peb 20591 list of tables page data sheet 2001-03-01 table 1 vip product family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2 peb 20590: u pn and s/t line interface . . . . . . . . . . . . . . . . . . . . . . . 11 table 3 peb 20591: u pn and s/t line interface . . . . . . . . . . . . . . . . . . . . . . . 12 table 4 iom-2000 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5 clock signals and dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6 power supply and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7 jtag boundary scan test interface (ieee 1149.1) . . . . . . . . . . . . . . 15 table 8 control bits in s/t mode on dr line . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 9 control bits in s/t mode on dx line . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 tap controller instruction codes overview . . . . . . . . . . . . . . . . . . . . 34 table 11 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12 i/o capacitances (except line interfaces and clocks) . . . . . . . . . . . . . 41 table 13 recommended crystal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14 iom-2000 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 15 jtag boundary scan timing values . . . . . . . . . . . . . . . . . . . . . . . . . 45
peb 20590 peb 20591 data sheet 1 2001-03-01 preface this document provides reference information on vip 1) (v ersatile i sdn p ort). organization of this document this data sheet is divided into 9 chapters. it is organized as follows: chapter 1 , introduction gives a general description of the vip, lists the key features, and presents some typical applications. chapter 2 , pin description lists pin locations with associated signals, categorizes signals according to function, and describes signals. chapter 3 , interface description describes the vip external interfaces. chapter 4 , operational description describes the vip operations reset, initialization, analog test loops and the monitoring of illegal code violations. chapter 5 , electrical characteristics contains the dc and ac specification and timing diagrams. chapter 6 , application hints provides information on external line interface circuitry in u pn and s/t mode, such as transformers and line protection. chapter 7 , package outlines chapter 8 , glossary chapter 9 , index 1) throughout this document the name vip will be used to refer to both chip versions peb 20590 and peb 20591.
peb 20590 peb 20591 data sheet 2 2001-03-01 preliminary your comments we welcome your comments on this document. we are continuously trying to improve our documentation. please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com please provide in the subject of your e-mail: device name (vip), device number (peb 20590), device version (version 2.1), and in the body of your e-mail: document type (data sheet), issue date (2001-03-01) and document revision number (ds4). related documentation data sheet for delic version 2.3 or higher (peb 20570, peb 20571)
peb 20590 peb 20591 introduction data sheet 3 2001-03-01 preliminary 1 introduction this chapter gives a general overview of the vip including a top-level block diagram and the logic symbol diagram, it lists the key features, and presents some typical applications. 1.1 overview vip (v ersatile i sdn p ort) is a highly-integrated multiple layer-1 transceiver ic connecting to u pn subscriber line interfaces (2-wire) and s/t subscriber or trunk line interfaces (4-wire). vip integrates the complete analog line interface circuitry as well as the transceiver logic required for eight full-duplex channels. typical vip applications include pbx line cards (u pn , s/t or mixed), and small pbxs. vip must be operated in combination with delic 1) , which is required for configuration and control/activation of vip ? s layer-1 transceivers. the communication path between the delic and the vip is the serial iom-2000 interface with a data rate of up to 12.288 mbit/s. delic also processes the signaling information of each vip channel by providing a dedicated hdlc controller per subscriber. for more information on delic and the iom-2000 interface, please refer to the delic-lc/-pb data sheet. 1) infineon technologies delic: dsp embedded line and port interface controller. the delic is available in two versions: peb 20570 and peb 20571.
peb 20590 peb 20591 introduction data sheet 4 2001-03-01 preliminary the vip is available in two different versions, which differ in the possible interface combinations: figure 1 top-level block diagram of the vip table 1 vip product family device available interfaces vip peb 20590 four channels are programmable to either s/t or u pn mode, and the other four channels can be operated in u pn mode only. vip-8 peb 20591 all eight channels are programmable to either s/t or u pn mode. maximum number of u pn and s/t channels u pn 876543210 s/t012344444 maximum number of u pn and s/t channels u pn 876543210 s/t012345678 vip_0002_block_diagram iom-2000 s/t or u pn . . . u pn and s/t transceiver iom-2000 interface analog line interface jtag central biasing delic clock
p-mqfp-80-1 data sheet 5 2001-03-01 versatile isdn port vip, vip-8 peb 20590 peb 20591 version 2.1 cmos type package peb 20590, peb 20591 p-mqfp-80-1 preliminary 1.2 vip key features vip is a universal isdn transceiver ic for different interface modes (s/t or u pn ). eight 2b+d line interfaces with full duplex transceivers ? s/t interfaces at 192 kbit/s with line transceivers according to itu-t i.430, etsi 300.012 and ansi t1.605 ? u pn interfaces at 384 kbit/s with line transceivers according to zvei standard ? receive timing recovery ? conversion between pseudo-ternary and binary codes ? conversion between u pn or s/t frames and iom-2000 frame structures ? execution of test loops ? frame alignment in trunk applications with maximum wander correction of 25 s ? u pn interface compatible to octat-p (peb 2096) 1) ? s/t interface compatible to quat-s (peb 2084) 2) iom-2000 interface to delic supporting up to three vips (24 channels) ? transceiver initialization and configuration ? control of layer-1 activation/deactivation ? exchange of command and status information signaling control for all vip channels by dedicated hdlc controllers in delic single 3.3 v power supply jtag ieee1149.1-compliant test interface with dedicated reset input note: u pn refers to a version of the u p0 interface (meeting the zvei standard) with a reduced loop length of up to 1.3 km, depending on the type of cable. 1) infineon technologies octat-p (peb 2096): octal transceiver for u pn -interfaces. 2) infineon technologies quat-s (peb 2084): quadruple transceiver for s/t-interface.
peb 20590 peb 20591 introduction data sheet 6 2001-03-01 preliminary 1.3 logic symbol diagrams figure 2 logic symbol peb 20590 (72 of 80 pins used) figure 3 logic symbol peb 20591 vip peb 20590 vip_0003_logic_symbol iom-2000 interface power supply analog / digital, reset jtag test interface clock signals 24 3 5 27 dedicated pins 6 s/t and u pn line interface 7 vip-8 peb 20591 vip_0006_8logic_symbol iom-2000 interface power supply analog / digital, reset jtag test interface clock signals 32 3 5 27 dedicated pins 6 s/t and u pn line interface 7
peb 20590 peb 20591 introduction data sheet 7 2001-03-01 preliminary 1.4 typical applications typical vip applications are pbx line cards (u pn , s/t or mixed), and small pbxs. the following figures illustrate sample configurations in which the vip shows its flexibility. figure 4 vip in mixed s/t and u pn line cards (e.g. 8 s/t and 16 u pn ) figure 5 vip in a small pbx solution vip_0004_line_card delic peb 20570 (peb 20571) pcm 4 x 32 ts iom-2000 signaling up to 2.048 mbit/s up to 4 x s/t 4 x u pn up to 4 x s/t 4 x u pn 8 x u pn memory p infineon c166 vip peb 20590 vip peb 20590 vip peb 20590 vip_0007_pbx delic-pb peb 20571 iom-2 memory p infineon c166 vip peb 20590 iom-2000 pcm lnc 2 mbit/s for service power supply hv-slic hv-slic hv-slic hv-slic slicofi-2 slicofi-2 central office 32 x t/r 4 x u pn 2 x s 2 x t up to 32 ts
peb 20590 peb 20591 introduction data sheet 8 2001-03-01 preliminary figure 6 delic-pb and vip in a pc card for 8/16 s/t interfaces delic-pb peb 20571 memory p infineon c166 vip-8 peb 20591 iom-2000 central office 6 x s 2 x t pita vip-8 peb 20591 8 x s pci switi pcm h.100/ h.110 (optional) (optional) vip_0008_pc_card
peb 20590 peb 20591 pin description data sheet 9 2001-03-01 preliminary 2 pin description the vip is available in an 80-pin plastic metric quad flat package (p-mqfp-80-1). this chapter presents a simple layout of the 80-pin mqfp package with pin and signal callouts and a table of signal definitions. 2.1 pin configuration (top view) figure 7 pin diagram, peb 20590 vip peb 20590 sr5b/li5b sr7a/li7a sr7b/li7b li6b li6a v dda v ssa n.c. n.c. v ssa v dda sx5a sx5b v ssa v dda sr5a/li5a sx7a sx7b v ssa v dda sr3b/ll3b sr1a/ll1a sr1b/ll1b ll2b ll2a v dda v ssa n.c. n.c. vip_add0 vip_add1 sx3a sx3b v ssa v dda sr3a/ll3a sx1a sx1b v ssa v dda scanen v ddd v ssd ll4b ll4a v dda v ssa n.c. n.c. v ddd v ssd tdi tms tck tdo powdn clk15-i clk-15-o 41 44 48 52 56 60 21 24 28 32 36 40 80 76 72 68 64 61 14 8 121620 dr iddq v ssd v ddd ll0b ll0a v dda v ssa n.c. n.c. v ssd v ddd dir refclk stat cmd dx dcl_2000 fsc inclk reset trst vip_0001_pinout p-mqfp-80-1
peb 20590 peb 20591 pin description data sheet 10 2001-03-01 preliminary (top view) figure 8 pin diagram, peb 20591 sx4b sx2a vip-8 peb 20591 sr5b/li5b sr7a/li7a sr7b/li7b sr6b/li6b sr6a/li6a v dda v ssa sx6b sx6a v ssa v dda sx5a sx5b v ssa v dda sr5a/li5a sx7a sx7b v ssa v dda sr3b/ll3b sr1a/ll1a sr1b/ll1b sr2b/ll2b sr2a/ll2a v dda v ssa sx2b vip_add0 vip_add1 sx3a sx3b v ssa v dda sr3a/ll3a sx1a sx1b v ssa v dda scanen v ddd v ssd sr4b/ll4b sr4a/ll4a v dda v ssa sx4a v ddd v ssd tdi tms tck tdo powdn clk15-i clk-15-o 41 44 48 52 56 60 21 24 28 32 36 40 80 76 72 68 64 61 14 8 12 16 20 dr iddq v ssd v ddd sr0b/ll0b sr0a/ll0a v dda v ssa sx0b sx0a v ssd v ddd dir refclk stat cmd dx dcl_2000 fsc inclk reset trst vip_0005_vip8_pinout p-mqfp-80-1
peb 20590 peb 20591 pin description data sheet 11 2001-03-01 preliminary 2.2 pin descriptions table 2 peb 20590: u pn and s/t line interface pin no. symbol in (i) out(o) during reset function 25 26 39 40 62 61 76 75 sr1a/li1a sr1b/li1b sr3a/li3a sr3b/li3b sr5a/li5a sr5b/li5b sr7a/li7a sr7b/li7b i / i/o i s/t receive channel 1, 3, 5, 7 / u pn transmit/receive channel 1, 3, 5, 7 12 13 28 27 48 47 73 74 li0a li0b li2a li2b li4a li4b li6a li6b i/o i u pn transmit/receive channel 0, 2, 4, 6 21 22 35 36 66 65 80 79 sx1a sx1b sx3a sx3b sx5a sx5b sx7a sx7b oo s/t transmit channel 1, 3, 5, 7 8, 9, 31, 32, 51, 52, 69, 70 n.c. - - n ot c onnected
peb 20590 peb 20591 pin description data sheet 12 2001-03-01 preliminary table 3 peb 20591: u pn and s/t line interface pin no. symbol in (i) out(o) during reset function 12 13 25 26 27 28 39 40 48 47 62 61 73 74 76 75 sr0a/li0a sr0b/li0b sr1a/li1a sr1b/li1b sr2a/li2a sr2b/li2b sr3a/li3a sr3b/li3b sr4a/li4a sr4b/li4b sr5a/li5a sr5b/li5b sr6a/li6a sr6b/li6b sr7a/li7a sr7b/li7b i / i/o i s/t receive channel / u pn transmit/receive channel 8 9 21 22 32 31 35 36 52 51 66 65 69 70 80 79 sx0a sx0b sx1a sx1b sx2a sx2b sx3a sx3b sx4a sx4b sx5a sx5b sx6a sx6b sx7a sx7b oo s/t transmit channel
peb 20590 peb 20591 pin description data sheet 13 2001-03-01 preliminary table 4 iom-2000 interface pin no. symbol in (i) out (o) during reset function 18 fsc i i iom-2000 f rame s yn c hronization 8 khz signal for iom-2000 frames 19 dcl_2000 i i iom-2000 d ata cl ock data clock from delic (3.072, 6.144 or 12.288 mhz in case of 1, 2 or 3 vips) 1 dr o o iom-2000 d ata r eceive data received on the line interface is sent to the delic 20 dx i i iom-2000 data transmit data to be transmitted on the line interface is received from the delic. 2 cmd i i iom-2000 c om m an d receives the commands from the delic. 3 stat o o iom-2000 stat us transmits the vip status information to the delic. 4 refclk o o iom-2000 ref erence cl oc k provides a 1.536 mhz reference clock (e.g. derived from central office in lt-t applications) to the delic
peb 20590 peb 20591 pin description data sheet 14 2001-03-01 preliminary table 5 clock signals and dedicated pins pin no. symbol in (i) out (o) during reset function 42 43 clk15-i clk15-o i o i o 15.36-mhz external crystal input 15.36-mhz external crystal output 17 inclk i i external reference cl oc k in put reference clock from vip or central office 33 34 vip_add0 vip_add1 ii vip add ress pins determines the sequential order of up to 3 vips in the iom-2000 frame for the 12- mhz case: vip_add(1:0) ? 00 ? = vip in 1st quarter of iom-2000 frame ? 01 ? = vip in 2nd quarter of iom-2000 frame ? 10 ? = vip in 3rd quarter of iom-2000 frame ? 11 ? = reserved for future connection of vip in 4th quarter of iom-2000 frame. currently only the lower addresses are available. (refer to iom-2000 description in delic-lc/ -pb data sheet) 16 iddq i i iddq test mode forces the line interface unit into power down mode for iddq testing. 41 powdn i i oscillator pow er d ow n switches the internal oscillator into power down mode (in case that 15.36-mhz input clock is provided by the delic) 5dir o o dir ection of transfer on u pn line interface indicates the direction of the data transfer (tx or rx) in u pn ping-pong mode (required for driving electronic transformers). 60 scanen i i scan en able if driven to ? 1 ? during device tests, a full scan of the vip is enabled.
peb 20590 peb 20591 pin description data sheet 15 2001-03-01 preliminary table 6 power supply and reset pin no. symbol in (i) out (o) during reset function 11, 24, 29, 38, 49, 63, 67, 72, 77 v dda ii power supply 3.3 v analog used for vip analog logic 6, 14, 45, 53 v ddd ii power supply 3.3 v digital used for vip digital logic 10, 23, 30, 37, 50, 64, 68, 71, 78 v ssa ii reference ground (0 v) analog 7, 15, 46, 54 v ssd ii reference ground (0 v) digital 44 reset i ? low ? system reset vip is forced to go into reset state. table 7 jtag boundary scan test interface (ieee 1149.1) pin no. symbol in (i) out (o) during reset function 58 tck i i t est c loc k provides a clock for jtag test logic. 57 tms i i t est m ode s elect (internal pull-up) a ?0? to ?1? transition on this pin is required to step through the tap controller state machine. 56 tdi i i t est d ata i nput (internal pull-up) in the appropriate tap controller state, test data or a instruction is shifted in via this line. 59 tdo o o t est d ata o utput in the appropriate tap controller state, test data or a instruction is shifted out via this line. 55 trst ii t est r e s e t (internal pull-up) provides an asynchronous reset to the tap controller state machine.
peb 20590 peb 20591 interface description data sheet 16 2001-03-01 preliminary 3 interface description the vip provides four types of external interfaces: u pn line interfaces, s/t line interfaces, an iom-2000 interface and a jtag boundary scan test interface. these interfaces are described in the following sections: 3.1 overview of interfaces the vip provides the following system interfaces: u pn line interfaces the vip provides up to 8 independent u pn line interfaces for connection of isdn terminals or dect base stations. s/t line interfaces the peb 20590 provides up to 4 independent s/t line interfaces (up to 8 for peb 20591). they can be operated in subscriber mode (lt-s) or trunk mode (lt-t). iom-2000 interface ? up to three vips can be connected to one delic via the iom-2000 interface. ? vip ? s transceivers are initialized and controlled by the delic. jtag boundary scan test interface ? the vip provides a standard test interface according to ieee 1149.1. ? user-specific instructions are implemented to generate periodic test patterns on the line. ? the tap controller has an own reset input. 3.2 u pn line interface the functionality is compatible to octat-p (peb 2096). 1:1 transformers are required. 3.2.1 frame structure the u pn interface uses a ping-pong technique for 2b+d data transmission over the line. u pn is always point-to-point. the frame structure of the data transfer between the exchange (pbx, lt) and the terminal (te) is depicted in figure 9 . the pbx starts a transmission every 250 s (burst repetition period). a frame transmitted by the exchange (pbx) is received by the terminal (te) after a given propagation delay t d . the terminal waits a minimum guard time ( t g = 5.2 s) while the line clears. then a frame is transmitted from the terminal to the pbx.
peb 20590 peb 20591 interface description data sheet 17 2001-03-01 preliminary the time between the end of reception of a frame from the te and the beginning of transmission of the next frame by the lt must be greater than the minimum guard time. the guard time in te is always defined with respect to the m-bit. figure 9 u pn interface frame structure data rates within a burst, the u pn data rate is 384 kbit/s using a 38-bit frame structure. during the 250-s burst repetition period, 4 d-bits, 16 b1-bits and 16 b2-bits are transferred in each direction, resulting in a full-duplex user data rate of 144 kbit/s. itd00823 lf b1 b2 8 1 8 d 4 8 8 b2 b1 m dc 2) 1 #bits 1 cv t s t cv t s t cv 1) 2) m channel superframe cv = code violation: for superframe synchronization t = transparent channel (2 kbit/s) s = service channel (1 kbit/s) dc balancing bit, only sent after a code violation in the m-bit position and in special configurations. timings: = burst repetition period = 250 = ine delay = 20.8 = guard time = 5.2 t r d t t g s s s maximum minimum g t t d r t d t 99 s lf-framing bit lt te/pt )
peb 20590 peb 20591 interface description data sheet 18 2001-03-01 preliminary control and maintenance bits u pn coding the coding technique used in the vip transceiver is half-bauded ami code with a 50 % pulse width (refer to figure 10 ). a code violation (cv) is caused by two successive pulses with the same polarity. bit description lf framing bit always logical ?1?. m m-bit final bit of the frame. four successive m-bits compose a superframe. three signals are carried in this superframe: cv code violation bit first bit of the superframe. used for superframe synchronization. s service bit third bit of the superframe. accessible via delic?s command/status interface. conveys test loop control information from the pbx to the te and reports transmission errors from the te to the pbx (far-end code violation). t t-bit 2nd and 4th bit of the superframe. accessible via delic?s command/status interface. carries the d-channel "available/blocked" information for the terminal and the dect synchronization information. dc dc balancing bit may be added to the burst to decrease dc offset voltage on the line after transmission of a cv in the m-bit position. vip issues this dc balancing bit when transmitting info 4 (line activated and synchronized), and when line characteristics indicate a potential decrease in performance. delic is able to enable or disable this feature (via the delic bbc command bit). binary value ami code with 50 % pulse width logical ? 0 ? neutral level logical ? 1 ? alternate positive and negative pulses
peb 20590 peb 20591 interface description data sheet 19 2001-03-01 preliminary figure 10 ami coding on the u pn interface in vip scrambling / descrambling b-channel data on the u pn interface is scrambled to ensure that the receiver at the subscriber terminal gets enough pulses for a reliable clock extraction (flat continuous power density spectrum), and to avoid periodical patterns on the line. the scrambler/ descrambler polynomial implemented in delic complies with itu-t v.27 and octat-p.
peb 20590 peb 20591 interface description data sheet 20 2001-03-01 preliminary 3.2.2 u pn transceiver the receiver input stages consist of an amplifier/equalizer, followed by a peak detector adaptively controlling the thresholds of the comparators and a digital oversampling unit. figure 11 transceiver functional blocks figure 12 equalizer effect the equalizer compensates the loss of amplitude of higher frequencies (see figure 12 ). in order to reach the best performance and range of the u pn transceiver, it is recommended to use the equalizer with automatic adaptation. rxpll and oversampling comparators peak detector receive clock up_trans.vsd receive data clk15-i lia lib transmit data e q u a l i z e r equi_up.vsd frequency amplitude cable
peb 20590 peb 20591 interface description data sheet 21 2001-03-01 preliminary to enable the filter of equalizer inside the vip, set bit ticcmr:fil to ? 1 ? (please refer to vip channel config description in delic-lc/-pb sw user ? s manual). the adaptive amplifier control of the equalizer should be set to automatic. set bit ticcmr:aac (1:0) to ? 00 ? (please refer to vip channel config description in delic-lc/-pb sw user ? s manual). 3.2.3 receive pll the receive pll (rxpll) recovers bit timing from a comparator output signal. note: the recommended setting for the receive pll is integral behaviour. this is enabled by setting bit ticcmr:pllint=?1? (please refer to vip channel config description in delic-lc/-pb sw user?s manual). comparator threshold. the comparator has a threshold of 80 % with respect to the signal stored by the peak detector. phase adjustment. the rxpll performs tracking after detecting phase shifts of the same polarity in four consecutive pulses. a phase adjustment is done by adding or subtracting 65 ns or 32.5 ns (one u pn oscillator period), programmable by the delic command bit ? plls ? (default ticcmr:plls ? 0 ? ), to or from the 384 khz receive data clock. 3.2.4 receive signal oversampling in order to further reduce the bit error rate in severe conditions, the vip performs oversampling of the received signal and uses majority decision logic. the process of receive signal oversampling is illustrated in figure 13 : each received bit is sampled 6 times at 15.36-mhz clock intervals inside the estimated bit window. the samples obtained are compared to a threshold of 50 % with respect to the signal stored by the peak detector. if at least ? n ? samples have an amplitude exceeding the 50 % threshold, a logical ? 1 ? is detected; otherwise a logical ? 0 ? (no signal) is assumed. the parameter ? n ? is programmed in steps of 2 in bits owin(2:0) of iom-2000 cmd register. note: the recommended setting for signal oversampling is ticcmr:owin =?011?. for detailed description please refer to delic-lc/-pb data sheet.
peb 20590 peb 20591 interface description data sheet 22 2001-03-01 preliminary . figure 13 receive signal oversampling on u pn interface 3.3 s/t line interface the functionality is compatible with that of quat-s (peb 2084). external protection circuitry is reduced, and 1:1 transformers are required.
peb 20590 peb 20591 interface description data sheet 23 2001-03-01 preliminary 3.3.1 frame structure the s/t interface uses two pairs of copper wires (dedicated to transmit and receive) for 2b+d data transfer. it builds a direct link between the vip and connected subscriber terminals or the central office. it supports point-to-point or point-to-multipoint modes. data and maintenance information is accessible by delic via the iom-2000 interface. figure 14 frame structure at reference points s and t (itu-t i.430) bit description f framing bit f = (0b) code violation, identifies a new frame (always positive pulse) l. dc balancing bit l. = (0b) number of binary zeros sent after the previous l. bit was odd d d-channel data signaling data specified by user e d-channel echo bit e = d if d-channel is not blocked, otherwise e = d . (zeros always overwrite ones) f a auxiliary framing bit see section 6.3 in itu i.430 n n = b1 b1-channel data user data b2 b2-channel data user data f a
peb 20590 peb 20591 interface description data sheet 24 2001-03-01 preliminary data rates the s/t transmission rate is 192 kbit/s (36 bits user data and 12 bits control and maintenance). frames are transmitted with a 2-bit offset in te/lt-t lt-s direction. s/t coding the coding technique used on the s/t interface is a full-bauded ami code with 100 % pulse width (refer to figure 15 ). figure 15 s/t interface line code (without code violation) a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted s s-channel data bit s1 and s2 channel data m multiframing bit m = (1b) start of new multi-frame binary value ami code with 100 % pulse width logical ? 0 ? alternate positive and negative pulses. there are two exceptions: the first binary ? 0 ? following the first dc balancing bit is of the same polarity as the dc bit, the f-bit is always at positive level (required code violations). logical ? 1 ? no line signal (0 v) bit description
peb 20590 peb 20591 interface description data sheet 25 2001-03-01 preliminary 3.3.2 s/t transceiver receiver characteristics the receiver input stages consist of a differential amplifier, followed by a peak detector and a set of comparators. additional noise immunity is achieved by digital oversampling after the comparators, meaning that the sampling of the received bit is controlled digitally and dependent on the mode (command register). the peak detector requires at most 2 s to reach the peak value while storing the peak level for at least 250 s. the data detection thresholds are set to 35 % of the peak voltage to increase the performance in extended passive bus configurations. however, they are never lower than 85 mv with respect to the line signal level in order to increase noise immunity. the level detector monitors the line input signals to detect whether an info signal is present. it is possible to indicate an incoming signal during activated analog loop. figure 16 receiver functional blocks 3.3.3 receive clock recovery the vip generates the internal clocks with a pll, that receives a 15.36-mhz signal via an on-chip oscillator either from an external crystal or from the delic. vip operating mode all clocks synchronized to lt-s or u pn mode iom-2000 interface data clock provided by the delic on dcl_2000 pin lt-t mode data clock provided by the central office 1.65 v
peb 20590 peb 20591 interface description data sheet 26 2001-03-01 preliminary 3.3.3.1 lt-s mode in the lt-s mode, the delic is the clock master to all terminals connected to the vip. in receive direction, two cases are distinguished, depending on the bus configuration: point-to-point or extended passive bus short passive bus. point-to-point or extended passive bus programmed by delic iom-2000 command bits: mosel(1:0) = ? 00 ? mode(2:0) = ? 011 ? the 192-khz receive bit clock is recovered (via pll) from the receive data stream on the s interface. shift between receive and transmit frame: according to itu-t i.430, the receive frame may be shifted by 2 to 8 bits with respect to the transmit frame. vip supports also other frame shifts, including 0. note: the recommended setting for point-to-point and extended passive bus in lt-s mode is ticcmr:owin=?101? and ticcmr:pd=?0?. for detailed description please refer to vip channel config command in the delic-lc/- pb sw user?s manual. short passive bus programmed by delic iom-2000 command bits: mosel(1:0) = ? 00 ? , mode(2:0) = ? 111 ? the 192-khz receive bit clock is identical to the transmit bit clock generated by division of the incoming iom-2000 data clock. shift between receive and transmit frame: the sampling instant for the receive bits is shifted by 4.6 s with respect to the transmit bit clock. according to itu-t i.430, the receive frame must be shifted (delayed) by two bits with respect to the transmit frame. note: if one vip has channels working in lt-s and u pn mode, then the f-bits appear on the s interface 6 u pn clocks (nominal case) later than the f-bits on the u pn lines (within the same sync frame). note: the recommended setting for short passive bus in lt-s mode is ticcmr:owin=?001? and ticcmr:pd=?0?. for detailed description please refer to vip channel config command in the delic-lc/-pb sw user?s manual.
peb 20590 peb 20591 interface description data sheet 27 2001-03-01 preliminary 3.3.3.2 lt-t mode programmed by delic iom-2000 command bits: mosel (1:0) = ? 00 ? , mode(2:0) = ? 001 ? in lt-t applications, the vip/delic system operates as slave to the central office clock. the 192-khz receive bit timing is recovered (via rxpll) from the receive data stream on the trunk line interface that was selected as clock source. the rxpll also provides a 1.536-mhz clock synchronous to the central office clock (adaptive timing recovery), which in lt-t applications is used to synchronize the delic clock generator via the iom-2000 refclk line; refer to figure 17 . the rxpll tracks every 250 s after detecting the phase between the framing bit transition (f/l-bit in s/t frame) of the receive signal and the recovered clock. a phase adjustment is done by adding or subtracting 65 ns or 130 ns to or from the 15.36-mhz clock depending on ? plls ? . if several vip or several s/t lines are operated in lt-t mode, only one trunk line may be selected to deliver the reference clock. the selection of this trunk line is programmed by the delic via iom-2000 command bits refsel(2:0) and exref. note: in lt-t mode, the transmit clock is identical to the recovered receive clock. note: the recommended setting for short passive bus in lt-t mode is ticcmr:owin=?101? and ticcmr:pd=?1?. for detailed description please refer to vip channel config command in the delic-lc/-pb sw user?s manual. figure 17 clock recovery in lt-t mode osc rxpll rxpll mux vip clock = 192 khz co co 192 khz 192 khz (up to 4 or 8 ch.) refclk 1.536 mhz 15.36 mhz vip-ltt-ref.vsd delic 15.36 mhz clock = 192 khz data fifo fifo dr 3.072/6.144/12.288 mhz dcl_2000
peb 20590 peb 20591 interface description data sheet 28 2001-03-01 preliminary jitter requirements in lt-t mode, itu-t i.430 specifies a maximum jitter in transmit direction of ? 7% to + 7 %, resulting in 730 ns peak-to-peak. this specification will be met by the vip provided that the master clock source is accurate within 100 ppm. 3.3.4 reference clock selection in lt-t mode in lt-t configurations, the delic receives the co reference clock via the xclk input pin, which is connected to vip ? s refclk output. the vip reference clock channel is programmed by the delic. the source may be either one of the 8 vip channels operated in lt-t mode or vip ? s inclk pin, when several vip ? s are connected to the iom-2000 interface (see figure 18 ). figure 18 lt-t reference clock channel selection for cascaded vips vip_0 vip_1 delic refclk dr vip_2 trunk (lt-t) ch_0 ch_7 ch_0 ch_7 ch_0 ch_7 inclk reference clock refclk inclk ch_0 ch_7 vip_n refsel exref inclk refclk xclk
peb 20590 peb 20591 interface description data sheet 29 2001-03-01 preliminary 3.3.5 receive signal oversampling the receive signal is oversampled within the receive clock period, and a majority logic is used to reduce the bit error rate in severe conditions. as illustrated in figure 19 , each received bit is sampled 29 times at 7.68-mhz clock intervals inside the estimated bit window. the samples obtained are compared against a threshold of 35% with respect to the signal stored by the peak detector. if at least a number of ? n ? samples have an amplitude exceeding the threshold, a logical ? 0 ? is detected; otherwise a logical ? 1 ? (no signal) is assumed. the parameter ? n ? is programmed by the owin command bits. figure 19 receive signal oversampling in s/t receiver 3.3.6 elastic buffer a buffer in the vip is designed as a wander-tolerant system, required in lt-t and lt-s modes. in lt-t mode, the vip is clock slave to the co, and the data clocks of the s/t interface and the iom-2000 interface have a time dependent phase relationship. the buffer compensates a maximum phase wander of 20 s. a slip detector indicates when this limit is exceeded. the ? slip ? bit in vip status register issues a warning to the delic when a slip of 20 s in either direction was detected. the vip buffers are reset to their default positions automatically. note: in case of frame slip, the phase relationship between the iom-2000 interface and the s/t interface is arbitrary. a re-alignment of the wander buffer after a slip may result in loss of data.
peb 20590 peb 20591 interface description data sheet 30 2001-03-01 preliminary 3.4 iom-2000 interface overview the iom-2000 interface connects up to three vips to delic. delic as the communication controller performs parts of the layer-1 protocol, which enables flexible and efficient operation of the vip. note: for detailed description of iom-2000, including the command and data interface, please refer to the delic data sheet. figure 20 overview of iom-2000 interface structure (example with one vip) iom-2000 description frame synchronization iom-2000 uses an 8-khz fsc. data interface data is transmitted via dx line from delic to vip with dcl_2000 rising edge. data is received via dr line from vip to delic, sampled with dcl_2000 falling edge. command/status interface configuration and control information of vip?s layer-1 transceivers is exchanged via cmd and stat lines. data/command clock data and commands for one vip are transmitted at 3.072 mhz. when delic drives 2 or 3 vips, the transmission rate is increased. reference clock in lt-t mode, the vip provides a reference clock synchronized to the exchange. in lt-s or u pn mode, delic is always the clock master to vip. bit 1 bit 0 bit 0 s/t: u pn : dx / dr: data transmit / receive in s/t mode f=3.072 mhz (2 x 8 x 192 kbit/s) data transmit / receive for u pn mode f=3.072 mhz (8 x 384 kbit/s) channel_0 channel_7 fsc dcl_2000 dx cmd dr stat vip delic . . . data ctrl data
peb 20590 peb 20591 interface description data sheet 31 2001-03-01 preliminary 3.4.1 iom-2000 frame structure 3.4.1.1 data interface on the isdn line side of the vip, data is ternary coded. since the vip contains logic to detect the level of the signal, only the data value is transferred via iom-2000 to delic. u pn mode in u pn mode, only data is sent via the iom-2000 data interface. s/t mode in s/t mode, data and control information is sent via iom-2000 data interface. every data bit has a control bit associated with it. thus, for each s/t line signal, 2 bits are transferred via dx and dr. bit0 is assigned to the user data, and bit1 carries control information. note: ?data? is always transmitted prior to ?ctrl? via dx/dr lines (refer to figure 21 ). table 8 control bits in s/t mode on dr line ctrl (bit1) data (bit0) function 0 0 logical ? 0 ? received on line interface 0 1 logical ? 1 ? received on line interface 1 0 received e-bit = inverted transmitted d-bit (e=d ) (lt-t only) 1 1 f-bit (framing) received; indicates the start of the s frame table 9 control bits in s/t mode on dx line ctrl (bit1) data (bit0) function 0 0 logical ? 0 ? transmitted on line interface 0 1 logical ? 1 ? transmitted on line interface 1 0 not used 1 1 f-bit (framing) transmitted; indicates the start of the s frame
peb 20590 peb 20591 interface description data sheet 32 2001-03-01 preliminary figure 21 iom-2000 data sequence (1 vip with 8 channels) note: 1. data transfer on iom-2000 interface always starts with the msb (related to b channels), whereas cmd and stat bits transfer always starts with lsb (bit 0) of any register 2. all registers follow the intel structure (lsb=2 0 , msb=2 31 ) 3. unused bits are don?t care (?x?) 4. the order of reception or transmission of each vip channel is always channel 0 to channel 7. a freely programmable channel assignment of multiple vips on iom-2000 (e.g., ch0 of vip_0, ch1 of vip_0, ch0 of vip_1, ch2 of vip_0,...) is not possible. fsc dcl ch0 bit0 ch1 bit0 (data) dx/dr 125 s 3.072 mhz lt-s mode: u pn mode: ch7 bit 23 (ctrl) f-bit ch0 bit1 ch1 bit0 (ctrl) ch1 bit1 (data) ch7 bit1 (data) ch1,3,5,7 in s mode (lt-s) ch0,2,4,6 in u pn mode ch7 bit0 (data) ch7 bit0 (ctrl) ch0 bit2 data data ctrl ch2 bit2 ch2 bit1 ch2 bit0 ch6 bit37 last bit of u pn frame last bit of lt-s frame
peb 20590 peb 20591 interface description data sheet 33 2001-03-01 preliminary figure 22 iom-2000 data order (3 vips with 24 channels) receive data channel shift in receive direction (dr), data of all iom-2000 channels (ch0...7 if one vip is used, ch0 ... ch23 if three vips are used) is shifted by 2 channels with respect to the transmitted data channels (dx), assuming a start of transmission of ch0 bit0 with the fsc signal. delic is transmitting ch0, while receiving ch2 via dr the same time, etc. dx ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch0 dr ch2 ch3 ch4 ch5 ch6 ch7 ch0 ch1 ch2 fsc dcl ch0 bit0 dx/dr 125 s 12.288 mhz f-bit ch24 bit0 (example for 24 channels in u pn mode) ch0 bit37 ch31 bit0 ch23 bit0 not used (don?t care) ch0 bit1 ch24 bit1 ch31 bit1 ch23 bit1 not used (don?t care) ch23 bit37 ch24 bit37 ch31 bit37 not used
peb 20590 peb 20591 interface description data sheet 34 2001-03-01 preliminary 3.5 jtag boundary scan test interface the vip provides ieee 1149.1-compatible boundary scan support to allow cost-effective board testing. it consists of: complete boundary scan test test access port (tap) controller five dedicated pins: tck, tms, tdi, tdo (according to jtag) and an additional trst pin to enable asynchronous resets to the tap controller one 32-bit idcode register specific functions for the analog line interface pins lina, b and sxna, b 3.5.1 tap controller the tap controller implements the state machine defined in the jtag standard ieee 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the tap controller supports 7 instructions: 5 standard instructions 2 additional user-specific instructions for transmitting continuous pulses at the line interfaces lina/b (60 khz) and sxna/b (120 khz) tap controller instructions extest. extest is used to verify the board interconnections. when the tap controller is in the state ? update dr ? , all output pins are updated with the falling edge of tck. when it has entered state ? capture dr ? the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. table 10 tap controller instruction codes overview code instruction function 0000 extest external testing 0001 intest internal testing 0010 sample/preload snap-shot testing 0011 idcode reading id code register 1111 bypass bypass operation 1000 user specific continuous pulses on lina and linb 1001 user specific continuous pulses on sxna and sxnb
peb 20590 peb 20591 interface description data sheet 35 2001-03-01 preliminary intest . intest supports internal chip testing. when the tap controller is in the state ? update dr ? , all inputs are updated internally with the falling edge of tck. when it has entered state ? capture dr ? the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 0011 (idcode) is the default value of the instruction register. sample/preload. sample/preload provides a snap-shot of the pin level during normal operation or is used to either preload (tdi) or shift out (tdo) the boundary scan test vector. both activities are transparent to the system functionality. note: the input pin clk15-i should not be evaluated. the input frequency (15.36 mhz) is not synchronous with tck (6.25 mhz); this may cause unpredictable snap-shots on the pin clk15-i. idcode. the 32-bit identification register is read out serially via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to ? 1 ? . the code for vip version 2.1 is ? 0010 ? . note: in the state ? test logic reset ? , the code ? 0011 ? is loaded into the instruction code register. bypass. a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. user-specific instructions. symmetric continuous pulses can be generated at pins lina/b (60 khz) and sxna/b (120 khz) to test the analog line interfaces. note: a 15.36 mhz crystal or an external 15.36 mhz clock signal on clk15-i is required for test pulse generation. version device code manufacturer code output 0010 0000 0000 0100 1111 0000 1000 001 1 --> tdo
peb 20590 peb 20591 operational description data sheet 36 2001-03-01 preliminary 4 operational description after some general remarks on the operation of the delic & vip chipset, the reset and the initialization procedure are described. the operation of analog test loops as well as the monitoring of illegal code violations are also part of this chapter. 4.1 general the delic & vip chipset provides all functionality required for data transmission over the u pn and the s/t interface, e.g., initialization and configuration, activation and deactivation, frame and multiframe synchronization. the u pn and s/t layer-1 state machines run on delic ? s dsp, performing activation/ deactivation, switching of loops and transmission of test pulse patterns. such actions can be initiated by info signals on the u pn and s/t lines, or by c/i codes sent by the p to delic, and transferred to vip via the iom-2000 command and status interface. all options and register settings are described in the delic data sheet. 4.2 reset at power-up, a reset pulse (reset = low active) of at least 1 s must be applied to reset the line interfaces of the vip. the source of the reset can be either the microprocessor, or the delic resind pin, which is a delayed reset signal. this assures that the vip is always reset simultaneously with the delic, and receives stable clock signals by the delic after reset. 4.3 initialization after hardware reset, each vip must be initialized and configured by iom-2000 commands. the following steps are required to initialize the vip: 1. delic: hardware reset (to synchronize the state machines, counters etc.) 2. vip: hardware reset 3. release resets 4. read version register from vip-cmd register (optional) (available from vip version v2.1 and higher) 5. program the vip if required, e.g. lt-t clock source 6. delic: program vip channel mode: u pn , lt-s or lt-t, closing test loops 7. delic: configure each vip receiver if required, e.g. oversampling, d-channel handling.
peb 20590 peb 20591 operational description data sheet 37 2001-03-01 preliminary 4.4 analog test loops different analog test loops may be switched in the vip near to the s/t or u pn line interfaces. no external u pn or s/t interface circuitry is required to close these loops: transparent analog loop, data forward path enabled non-transparent analog loop, data forward path blocked external transparent analog loop, for board testing. initialization of test loops unlike the lt-t state machine, the lt-s and u pn state machines in the delic do not support loops. consequently neither the c/i commands nor indications are provided by the mailbox protocol. a loop can be programmed by setting bits ticcmr:loop and ticcmr:exlp for the respective channel. note: for detailed description please refer also to the application note ? test loops in the vip ? . transparency in u pn or lt-s mode, the user may output the loop-back data also transparently onto the line interface. the selection is performed via iom-2000 tx_en command. external analog loops are activated by exlp command bit (refer to chapter 6.3 ). note: in order to guaranty that the loop is closed tx_en must be set to one for the u pn interface 4.5 monitoring of code violations any code violation on the s/t interface (according to ansi t1.605), or code violations at positions other than the f-bit or m-bit in the u pn frame result in vip status bit fecv being sent to delic. the check is performed once in every multiframe (every 20th 4-khz s/t frame). to synchronize the checking, delic must issue the sh_fsc bit every 40th iom frame.
peb 20590 peb 20591 electrical characteristics data sheet 38 2001-03-01 preliminary 5 electrical characteristics this chapter contains the dc and ac specifications (as far as available) and timing diagrams. 5.1 absolute maximum ratings note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 5.2 operating range note: in the operating range the functions given in the circuit description are fulfilled. parameter symbol limit values unit storage temperature t stg ? 65 to 150 c ic supply voltage v dd ? 0.3 to 4.6 v dc input voltage (except i/os) v i ? 0.3 to 6.0 v dc output voltage (including i/os); output in high or low state v o ? 0.3 to v dd + 0.3 v dc output voltage (including i/os); output in tri-state v i, v o ? 0.3 to 6.0 v esd robustness 1) hbm: 1.5 k ? , 100 pf 1) according to mil-std 883d, method 3015.7 and esd ass. standard eos/esd-5.1-1993. the sx pins are not protected against voltage stress > 1500 v (versus v s or gnd). v esd,hbm 2000 v parameter symbol limit values unit min. max. power supply voltage 5% v dd 3.13 3.47 v ground v ss 00v voltage applied to input pins v in 0 v dd +0.3 v operating temperature t a 070 c
peb 20590 peb 20591 electrical characteristics data sheet 39 2001-03-01 preliminary 5.3 dc characteristics v dd = 3.3 v 0.17 v, t a = 0 to 70 c table 11 dc characteristics parameter symbol limit values unit test condition min. max. all digital pins except lina,b; sxna,b; srna,b; clk15-i,-o l-input voltage v il 0.8 v h-input voltage v ih 2.0 v dd + 0.3 v l-output voltage v ol 0.45 v iout = 2ma h-output voltage v oh 2.4 v iout = 2 ma input leakage current i li 1 a0 v v in v dd ; not specified for pins dir and refclk. tdi; tms; trst input leakage current high i lih 1 a v in = v dd input leakage current low i lil 10 300 a v in = 0 v; internal pull-up resistor lina,b transmitter output amplitude v x 2.24 3.08 v u pn - transmitter output amplitude receiver input impedance z r 10 k ? receiver input impedance, transmitter inactive sxna,b absolute value of output pulse amplitude ( v sxna ? v sxnb ) v x 1.05 1.05 1.16 1.23 v v r l = 50 ? r l = 400 ?
peb 20590 peb 20591 electrical characteristics data sheet 40 2001-03-01 preliminary transmitter output current i x 21.0 1) 26.8 2) ma r l = 5.6 ? transmitter output impedance z x acc. to itu-t i.430 0 k ? ? inactive or during binary one, 0 v v in v dd during binary zero 1) nominal value determined by fuses 2) absolute current limit resulting from the s interface specification clk15-i h-input voltage v ih 1.2 v dd + 0.3 v l-input voltage v il 0.4 v clk15-o h-output voltage v oh 2.4 v f = 0 l-output voltage v ol 0.45 v f = 0 supply current operational supply current, peak value i cc 30 +n 27.5 +m 47.5 ma peak supply current, v dd = 3.3 v n = number of s/t interfaces activated m = number of u pn interfaces activated operational supply current, mean (typical) value i cc 18 +n 8.5 +m 6.5 ma mean supply current, v dd = 3.3 v n = number of s/t interfaces activated m = number of u pn interfaces activated table 11 dc characteristics (cont ? d) parameter symbol limit values unit test condition min. max.
peb 20590 peb 20591 electrical characteristics data sheet 41 2001-03-01 preliminary 5.4 capacitances t a = 25 c; v dd = 3.3 v 0.17 v, v ss = 0 v, f c = 1 mhz, unmeasured pins grounded 5.5 recommended 15.36-mhz crystal parameters the user has two options to supply the vip 15.36-mhz input clock: via a standard 15.36-mhz crystal or via an external source, e.g. connecting the delic output pin l1_clk (duty cycle of 40:60 or better is required). the on-chip oscillator must be powered-down via pin powdn. note: it is recommended to supply the vip 15.36-mhz input clock via the delic. in case a crystal (serial resonance) is connected, it should meet the requirements shown in table 13 . figure 23 recommended oscillator circuit table 12 i/o capacitances (except line interfaces and clocks) parameter symbol limit values unit test condition min. max. pin capacitance c i/o 7pf table 13 recommended crystal parameters parameter symbol typical values unit test condition motional capacitance c 1 20 ff shunt capacitance c 0 7pf external load capacitance c l 30 pf resonance resistance r r 65 ? frequency calibration tolerance 100 ppm its11110 15.36 mhz clk-15 clk-15o n.c. oscillator external signal crystal oscillator mode driving from external source 100 ppm c ld ld c c ld =2 . l c - c i/o clk-15o clk-15
peb 20590 peb 20591 electrical characteristics data sheet 42 2001-03-01 preliminary 5.6 ac characteristics t a = 0 to 70 c; v dd = 3.3 v 0.17 v note: timing measurements are made at 2.0 v for a logical 1 ? and at 0.8 v for a logical ? 0 ? . figure 24 input/output wave form for ac tests 5.7 refclk 5.8 u pn interface parameter symbol limit values unit comment min. max. high phase of clock t wh 40 ns delay of falling edge after falling edge of inclk low phase of clock t wl 40 ns delay of rising edge after rising edge of inclk clock period t p 651 ns during pll adjustment this value could change parameter symbol limit values unit comment min. max. dir delay from dcl_2000 rising edge t dir 60 ns 50 pf
peb 20590 peb 20591 electrical characteristics data sheet 43 2001-03-01 preliminary 5.9 iom-2000 interface figure 25 iom-2000 timing table 14 iom-2000 interface timing parameter symbol limit values unit notes min. typ. max. dr delay from dcl_2000 rising edge t dr 38 ns stat delay from dcl_2000 rising edge t stat 38 ns cmd setup time to dcl_2000 falling edge t cmds 10 ns cmd hold time to dcl_2000 falling edge t cmdh 10 ns dcl_2000 dx dr cmd stat ch0 ch1 ch2 ch3 ch2 ch3 ch4 ch5 fsc t cmds t cmdh t dr t stat t dxs t dxh iom_2000.vsd t fscs
peb 20590 peb 20591 electrical characteristics data sheet 44 2001-03-01 preliminary 5.10 jtag boundary scan test interface figure 26 jtag timing fsc setup time before dcl_2000 rising edge t fscs -2 10 ns fsc hold time after dcl_2000 falling edge t fsch 70 ns not shown in figure 25 dx setup time before dcl_2000 falling edge t dxs 10 ns dx hold time after dcl_2000 falling edge t dxh 10 ns table 14 iom-2000 interface timing parameter symbol limit values unit notes min. typ. max.
peb 20590 peb 20591 electrical characteristics data sheet 45 2001-03-01 preliminary 5.11 u pn transmitter performance the vip fulfills the electrical requirements of the u pn interface for loop lengths, depending on the cable quality: 5.12 s/t transmitter performance cable 0.6 mm, 120 nf/km table 15 jtag boundary scan timing values parameter symbol limit values unit min. max. test clock period t tcp 100 ns test clock period low t tcpl 50 ns test clock period high t tcph 50 ns tms setup time to tck t mss 10 ns tms hold time from tck t msh 10 ns tdi setup time to tck t dis 10 ns tdi hold time from tck t dih 10 ns tdo valid delay from tck t dod 30 ns adaptive equalizer switching is enabled aac(1:0) = ? 0x ? and fil = 1 in delic iom-2000 command register cable loop length j-y (st) y 2 2 0.6 up to 1 km awg 26 up to 1.3 km configuration condition distance te-te distance te-lt point-to-point no noise ? 1000 200 / 2000 khz 100 mvpp ? 950 ext. passive bus no noise 120m 750m (roundtrip < 2 s) 200 / 2000 khz 100 mvpp 120m 550m
peb 20590 peb 20591 application hints data sheet 46 2001-03-01 preliminary 6 application hints this chapter provides some additional information on how to use the vip. the first section describes some external circuitry: recommended line transformers, resistors and capacitors. different wiring configurations in user premises are depicted for the lt- s mode, and the different loops that can be closed in the vip via the delic are also presented in the following sections. 6.1 vip external circuitry 6.1.1 recommended line transformers the vip is connected to the u pn or s/t lines via 1:1 transformers. the line side (primary side) of the transformer could be center-tapped for the phantom power supply. reference model parameters of the transformers are shown below. u pn transformer primary to secondary transformer ratio: 1:1 primary total dc resistance: r 4..8 ? primary inductance: l m > 2.1 mh = 20 % primary inductance with secondary short circuited: l p < 22 h coupling capacitance: c k < 150 pf s/t transformer primary to secondary transformer ratio: 1:1 primary total dc resistance: r 2 ? = primary inductance: l m > 30 mh primary inductance with secondary short circuited: l p < 6 h coupling capacitance: c k < 80 pf figure 27 1:1 transformer model l p r l m c k 1:1 ideal transformer line side vip-trafo-model.vsd
peb 20590 peb 20591 application hints data sheet 47 2001-03-01 preliminary 6.1.2 u pn interface external circuitry a transformer, external resistors and two capacitors (100 nf and 0.33 f) are connected externally to the line interface pins lina,b. voltage overload protection is achieved by adding clamping diodes (see figure 28 ). figure 28 external transceiver circuitry of the vip in u pn mode note: the resistor values in figure 28 are optimized for an ideal transformer ( r cu =0). the 0.33-f capacitance will be verified during system tests. 6.1.3 s/t interface external circuitry the vip needs some external circuitry to achieve impedance matching, overvoltage protection and electromagnetic compatibility (emc) for its connection to the 4-wire s/t interface. the configuration is shown in figure 29 . figure 29 overview of external circuitry of the vip in s/t mode note: the actual values of the external resistors depend on the transformer selected. the resistor values are optimal for an ideal transformer ( r cu = 0). line termination ( r t ) is usually applied to the nt and last wall outlet on the s bus only. ext_u_tr.vsd vip u pn transceiver 10 ? 50 ? 10 ? 1:1 50 ? 100 nf 0.33 f vdd u pn s/t transmitter s/t receiver i max = 26.8 ma (spec.) 1,1 v zw = 100 ? r t = 100 ? 0,75 v 1:1 0,75 v 10% 1:1 external circuitry external circuitry ext_s i max = 21 ma (typ.) r t = 100 ?
peb 20590 peb 20591 application hints data sheet 48 2001-03-01 preliminary transmitter. dedicated external resistors (10 ? 12.5 ? ) are required for the transmitter in order to adjust the output voltage to the pulse mask (nominal 750 mv according to itu-t i.430), meet the output impedance of a minimum of 20 ? (transmission of a binary ? 0 ? according to itu-t i.430). figure 30 external s/t transmitter circuitry receiver. at the receiver, 8 k ? overall resistance is needed in each receive path. it is recommended to use two resistors per line, as shown in figure 31 . this makes it possible to place a high resistance between the transformer and the diode protection circuit (required to pass 96-khz input impedance test of itu-t i.430). the remaining resistor protects the vip receiver from input current peaks. figure 31 external s/t receiver circuitry s/t transmitter overvoltage protection 10...12.5 ? s-interface connector 1:1 sxna sxnb gnd ext_s_tr.vsd dc point v dd 10...12.5 ? diodes: 1n4151 (or similar) s/t receiver overvoltage protection 1.2 k ? s-interface connector 1:1 srna srnb 1.2 k ? 6.8 k ? 6.8 k ? gnd ext_s_re.vsd dc point v dd diodes: 1n4151 (or similar) *) *) *) up to 47 pf (for additional noise reduction if required)
peb 20590 peb 20591 application hints data sheet 49 2001-03-01 preliminary 6.2 wiring configurations in lt-s mode figure 32 wiring configurations in user premises (lt-s mode) vip_0009_busconf_lts tr tr ... short passive bus < 100-200 m * te1 te8 vip lt-s scout-s scout-s tr tr ... extended passive bus 500 m te1 te8 vip lt-s scout-s scout-s < 25-50 m * tr: terminating resistor tr point-to-point configurations < 1000 m te1 vip lt-s scout-s tr * see itu i.430 < 10m < 10m
peb 20590 peb 20591 application hints data sheet 50 2001-03-01 preliminary 6.3 loop modes the following figure shows the different loops that can be closed in the vip. loops are programmed by the delic using the command bits loop, exlp and tx_en. figure 33 internal and external loop-back modes exlp loop tx_en analog line driver analog transmitter analog receiver mux dx dr external vip internal analog loop circuitry iom-2000 1 0 tx rx
peb 20590 peb 20591 package outlines data sheet 51 2001-03-01 7 package outlines p-mqfp-80-1 (plastic metric quad flat package) gpm05249 smd = surface mounted device sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm
peb 20590 peb 20591 glossary data sheet 52 2001-03-01 preliminary 8 glossary ami alternate mark inversion ansi american national standardization institute cmos complementary metal oxide semiconductor co central office dc direct current dect digital european cordless telecommunication delic dsp embedded line and port interface controller (peb 20570, peb 20571) emc electromagnetic compatibility etsi european telephone standards institute hdlc high-level data link control ieee institute of electrical and electronic engineers info u- and s-interface signal as specified by ansi/etsi i/o input/output iom-2 isdn-oriented modular 2nd generation iom-2000 proprietary isdn inferface for connection of vip to delic isdn integrated services digital network itu international telecommunications union octat-p octal transceiver for u pn -interfaces (peb 2096) lt-s line termination-subscriber lt-t line termination-trunk pll phase-locked loop pbx private branch exchange quat-s quadrupletransceiver for s/t-interface (peb 2084) s/t two-wire pair interface tap test access port u pn two-wire interface zvei zentralverband elektrotechnik und elektroindustrie e.v.
peb 20590 peb 20591 index data sheet 53 2001-03-01 preliminary 9 index a ac characteristics 42 analog test loops 37 application hints 46 applications 7 b block diagram 4 c capacitances 41 clock synchronization 25 crystal parameters 41 d dc characteristics 39 e extended passive bus 26 external circuitry 46 f features (vip) 5 i initialization 36 interface iom-2000 interface 30 jtag boundary scan test inter- face 34 overview 16 s/t line interface 22 u pn line interface 16 iom-2000 frame structure 31 iom-2000 interface 30 j jitter requirements 28 jtag boundary scan test interface 34 jtag boundary scan test interface timing 42 l logic symbol peb 20590 6 peb 20591 6 loop modes 50 o operating modes 25 operating range 38 operational description 36 oscillator circuit 41 p package 51 pin descriptions 9 clock signals and dedicated pins 14 iom-2000 interface 13 jtag boundary scan test inter- face 15 power supply and reset 15 upn and s/t line interface 12 u pn and s/t line interface 11 pin diagram peb 20590 9 peb 20591 10 p-mqfp-80-1 51 product family (vip) 4 r reference clock selection 28 reset 36 s s/t coding 24 s/t line interface 22 data rates 24 elastic buffer 29 external circuitry 47 frame structure 23 receive signal oversampling 29
peb 20590 peb 20591 index data sheet 54 2001-03-01 preliminary s/t transceiver 25 receive clock recovery 25 receiver characteristics 25 s/t transformer 46 s/t transmitter performance 45 short passive bus 26 system integration 7 t tap controller 34 u u pn coding 18 u pn line interface 16 control and maintenance bits 18 external circuitry 47 frame structure 16 u pn scrambling/descrambling 19 u pn transceiver 20 receive pll 21 receive signal oversampling 21 u pn transformer 46 u pn transmitter performance 45 w wiring configurations in lt-s mode 49
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